1. Field
Example embodiments relate to the test of semiconductor memory devices, and more particularly, to a semiconductor memory device including a mount test circuit that may be capable of reducing a test time, and a mount test method thereof.
2. Description of Related Art
In semiconductor memory devices, for example DRAM, there may be a need for read and write operations of data to be precise. There may be a need to have a reduced number of defective cells on a chip. However, semiconductor devices may be highly integrated. Consequently, the number of memory cells integrated in one chip may increase. Thus, despite the development of semiconductor device manufacturing processes, the likelihood of defective cell occurrence within the chip may increase. Unless a precise test for these defective cells is performed, it may be difficult to achieve an acceptable level of reliability with semiconductor memory devices.
In a test operation of semiconductor memory devices, for example, when the test per memory cell should be performed in a highly integrated semiconductor memory device, a test time may be lengthened and cost may increase. In order to lessen the test time for semiconductor memory device, many devices and methods are under development. A parallel bit test method may be used to reduce the test time.
The parallel bit test method may employ an XOR (exclusive OR) or XNOR (exclusive NOR) logic circuit. For example, the same data may be written to a plurality of memory cells, and then in a read operation for the data, a logical operation may be performed through an XOR or XNOR logical circuit. At this time, when data of the same logic state is read, a decision of pass may be given, and when data having even one different logic state is read, it may be regarded as a failure in the test.
Tests of semiconductor memory devices like those described above may have been performed only on devices in a wafer state or package state. However, the test may be required even when the semiconductor memory devices may be mounted on a PCB (printed circuit board) as a memory module. In a test of such a real system (hereinafter, referred to as ‘mount test’), it may be impossible to perform the test by the same method as the conventional wafer state or package state since the semiconductor memory devices may be operating.
In particular, when the mount test employing the parallel bit test method is performed, problems may occur. In other words, the mount test for the semiconductor memory devices may be performed at a normal speed and a fail signal, which may be generated through a data comparison, may be passed through a logic circuit such as XOR etc., and may produce a delay. Thus, it may be difficult to properly process the fail signal in real time. As a possible solution to the problem, a fail signal processing method which may generate subsequent data as a high impedance (Hi-Z) in the case of fail occurrence has been introduced. That is, in the fail occurrence, a fail processing operation may be performed through a floating of a data output path. This is described referring to FIG. 1, as follows.
FIG. 1 illustrates a test circuit for a mount test according to a conventional art.
As shown in FIG. 1, in a conventional mount test circuit, two memory blocks, 12 and 14, may be selected from a memory array 10, which may have a plurality of memory blocks, and may be tested simultaneously. For the test, a comparison unit 20 and a fail processing unit 30 may be used. Additionally, data may be written to the two memory blocks 12 and 14 simultaneously.
The comparison unit 20 may compare data AD0˜AD3 of the first memory block 12 with data BD0˜BD3 of the second memory block 14, and may decide whether a fail occurs. The comparison unit 20 may have the same configuration as a comparator of general parallel test circuit. For example, whether or not the data AD0˜AD3 and the data BD0˜BD3 are identical may be determined by employing a plurality of XOR logic circuits 22, 23, 24 and 25 and an OR logic circuit 26 in the comparison unit. The comparison unit 20 may generate a pass signal as a decision signal DS when the data is identical, and the comparison unit 20 may generate a fail signal as a decision signal DS when the data is not identical.
The fail processing unit 30 may output data BD0˜BD3 of one predetermined memory area, i.e., second memory area, to the outside through an output buffer (not shown) when a pass signal is applied from the comparison unit 20. When the fail signal is applied from the comparison unit 20, output data outputted subsequently may be set to a state of high impedance HZ. In other words, a data output path through which the output data is outputted may become floating. Here, the high impedance state may indicate neither a logic state of data 0 nor a logic state of data 1. However, such conventional mount test technology may cause several problems in an actual system. As an example, a read operation may be generated in a specific area where a write operation for the test has not been performed. Thus, even though a fail has not actually occurred, a fail signal may generated. Such problem may be caused when a cache memory has been used or a system area has been contained therein, etc. For example, when the cache memory is used, a write operation may be performed to fill a cache line and unknown data of area may be read by an initial dummy read operation, etc., thus causing a fail. Furthermore, in a system area such as an operating system etc., unknown read data may be used as test data by the dummy read operation of the system area etc. and a fail may be caused. Thus, it may be difficult to perform the normal test.